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electrical specifications subject to change electrical specifications subject to change ltc2203/ltc2202 1 22032p fea tures descriptio u applica tio s u typical applica tio u 16-bit, 25msps/10msps adc the ltc ? 2203/ltc2202 are 25msps/10msps, sampling 16-bit a/d converters designed for digitizing high frequen - cy, wide dynamic range signals with input frequencies up to 400mhz. the input range of the adc can be optimized with the pga front end. the ltc2203/ltc2202 are perfect for demanding ap - plications, with ac performance that includes 81.4db snr and 100db spurious free dynamic range (sfdr). maximum dc specs include 4lsb inl, 1lsb dnl (no missing codes). a separate output power supply allows the cmos output swing to range from 0.5v to 3.6v. a single-ended clk input controls converter operation. an optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. telecommunications receivers cellular base stations spectrum analysis imaging systems ate sample rate: 25msps/10msps 81.6db snr and 100db sfdr (2.5v range) sfdr >83db at 70mhz (1.667v p-p input range) pga front end (2.5v p-p or 1.667v p-p input range) 400mhz full power bandwidth s/h optional internal dither optional data output randomizer single 3.3v supply power dissipation: 210mw/140mw clock duty cycle stabilizer out-of-range indicator pin compatible family 25msps: ltc2203 (16-bit) 10msps: ltc2202 (16-bit) 48-pin (7mm 7mm) qfn package , l tc and lt are registered trademarks of linear t echnology corporation. a ll other trademarks are the property of their respective owners. C + s/h amp correction logic and shift register output drivers 16-bit pipelined adc core internal adc reference genera tor 1.25v common mode bias volt age clock/duty cycle control clk pga shdn dith mode rand v cm analog input 22032 t a01 d15 ? ? ? d0 cmos outputs 0.5v to 3.6v 3.3v 3.3v sense ognd ov dd 2.2f 1f 1f 1f 1f v dd gnd adc control inputs ain + ain C of clkout+ clkoutC oe frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 go7 ltc2203: 128k point fft, f in = 5.1mhz, C1dbfs, pga = 0
prepared for ltc2203/ltc2202 2 22032p absolute axi u r at i g s w w w u for a tio package/order i u u w co verter characteristics u parameter conditions min typ max units resolution (no missing codes) 16 integral linearity error differential analog input (note 5) t a = 25c 1.2 4.0 lsb integral linearity error differential analog input (note 5) 1.5 4.5 lsb differential linearity error differential analog input 0.3 1 lsb offset error (note 6) 2 8 mv offset drift 10 v/ c gain error external reference 0.2 1.5 %fs full-scale drift internal reference 30 ppm/c external reference 15 ppm/c transition noise external reference 1.95 lsb rms supply voltage (v dd ) ................................... C 0.3v to 4v digital output ground voltage (ognd) ........ C 0.3v to 1v analog input voltage (note 3) ..... C 0.3v to (v dd + 0.3v) digital input voltage .................... C 0.3v to (v dd + 0.3v) digital output voltage ................ C 0.3v to (ov dd + 0.3v) power dissipation ............................................ 2000mw operating temperature range ltc2203c/LTC2202C ............................... 0c to 70c ltc2203i/ltc2202i ............................. C 40c to 85c storage temperature range .................. C 65c to 150c digital output supply voltage (ov dd ) .......... C 0.3v to 4v order part number uk part* marking *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for parts speci?ed with wider operating temperature ranges. ltc2203c LTC2202C ltc2203i ltc2202i ov dd = v dd (notes 1 and 2) the denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. (note 4) xxxxx xxxxx exposed pad is gnd (pin 49) must be soldered to pcb board t jmax = 125c, ja = 29c/w top view uk p ackag e 48-lead (7mm 7mm) plastic qfn sense 1 v cm 2 v dd 3 v dd 4 gnd 5 ain + 6 ain C 7 gnd 8 gnd 9 clk 10 gnd 11 v dd 12 36 ovdd 35 d11 34 d10 33 d9 32 d8 31 ognd 30 clkout+ 29 clkoutC 28 d7 27 d6 26 d5 25 ovdd 48 gnd 47 pga 46 rand 45 mode 44 oe 43 of 42 d15 41 d14 40 d13 39 d12 38 ognd 37 ovdd v dd 13 v dd 14 gnd 15 shdn 16 dith 17 d0 18 d1 19 d2 20 d3 21 d4 22 ognd 23 ovdd 24 49 order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/
ltc2203/ltc2202 3 22032p a alog i put u u ltc2203 ltc2202 symbol parameter conditions min typ max min typ max units snr signal-to-noise ratio 1mhz input (2.5v range, pga = 0) 81.6 81.6 dbfs 1mhz input (1.667v range, pga = 1) 79.4 79.4 dbfs 5mhz input (2.5v range, pga = 0) 80.5 81.6 80.5 81.6 dbfs 5mhz input (1.667v range, pga = 1) 79.4 79.4 dbfs 12.5mhz input (2.5v range, pga = 0) 81.4 81.4 dbfs 12.5mhz input (1.667v range, pga = 1) 79.3 79.3 dbfs 30mhz input (2.5v range, pga = 0) 80.8 80.8 dbfs 30mhz input (1.667v range, pga = 1) 77.8 78.9 77.8 78.9 dbfs 70mhz input (2.5v range, pga = 0) 78.3 78.3 dbfs 70mhz input (1.667v range, pga =1 ) 77.2 77.2 dbfs sfdr spurious free 1mhz input (2.5v range, pga = 0) 100 100 dbc dynamic range 1mhz input (1.667v range, pga = 1) 100 100 dbc 2 nd or 3 rd harmonic 5mhz input (2.5v range, pga = 0) 92 100 tbd 95 dbc 5mhz input (1.667v range, pga = 1) 100 100 dbc 12.5mhz input (2.5v range, pga = 0) 95 90 dbc 12.5mhz input (1.667v range, pga = 1) 100 95 dbc 30mhz input (2.5v range, pga = 0) 90 85 dbc 30mhz input (1.667v range, pga = 1) 90 95 90 95 dbc 70mhz input (2.5v range, pga = 0) 85 85 dbc 70mhz input (1.667v range, pga = 1) 90 90 dbc sfdr spurious free 1mhz input (2.5v range, pga = 0) 100 100 dbc dynamic range 1mhz input (1.667v range, pga = 1) 100 100 dbc 4 th harmonic 5mhz input (2.5v range, pga = 0) 96 100 96 100 dbc or higher 5mhz input (1.667v range, pga = 1) 100 100 dbc 12.5mhz input (2.5v range, pga = 0) 100 100 dbc 12.5mhz input (1.667v range, pga = 1) 100 100 dbc 30mhz input (2.5v range, pga = 0) 100 100 dbc 30mhz input (1.667v range, pga = 1) 94 100 100 dbc 70mhz input (2.5v range, pga = 0) 90 90 dbc 70mhz input (1.667v range, pga = 1) 90 90 dbc the denotes the speci?cations which apply over the full operating temperature range, other wise speci?cations are at t a = 25c. (note 4) dy a ic accuracy u w the denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. a in = C 1dbfs. (note 4) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 3.135v v dd 3.465v 1.667 or 2.5 v p-p v in, cm analog input common mode differential input (note 7) 1 1.25 1.5 v i in analog input leakage current 0v a in + , a in C v dd C1 1 a i sense sense input leakage current 0v sense v dd C3 3 a i mode mode pin pull-down current to gnd 10 a i lvds lvds pin pull-down current to gnd 10 a c in analog input capacitance sample mode enc + < enc C 10.9 pf hold mode enc + > enc C 1.2 t ap sample-and-hold tbd ns acquisition delay time t jitter sample-and-hold 200 fs rms acquisition delay time jitter cmrr analog input 1v < (a in + = a in C ) <1.5v 80 db common mode rejection ratio bw-3db full power bandwidth 400 mhz
prepared for ltc2203/ltc2202 4 22032p ltc2203 ltc2202 symbol parameter conditions min typ max min typ max units s/(n+d) signal-to-noise 1mhz input (2.5v range, pga = 0) 81.5 81.5 dbfs plus distortion ratio 1mhz input (1.667v range, pga = 1) 79.3 79.3 dbfs 5mhz input (2.5v range, pga = 0) 80.4 81.5 80.4 81.5 dbfs 5mhz input (1.667v range, pga = 1) 79.3 79.3 dbfs 12.5mhz input (2.5v range, pga = 0) 81.3 81.3 dbfs 12.5mhz input (1.667v range, pga = 1) 79.2 79.2 dbfs 30mhz input (2.5v range, pga = 0) 80.6 80.6 dbfs 30mhz input (1.667v range, pga = 1) 77.7 78.6 77.7 78.6 dbfs 70mhz input (2.5v range, pga = 0) 78.1 78.1 dbfs 70mhz input (1.667v range, pga = 1) 77 77 dbfs sfdr 1mhz input (2.5v range, pga = 0) 105 105 dbfs 1mhz input (1.667v range, pga = 1) 105 105 dbfs 5mhz input (2.5v range, pga = 0) 105 105 dbfs 5mhz input (1.667v range, pga = 1) 105 105 dbfs 12.5mhz input (2.5v range, pga = 0) 105 105 dbfs 12.5mhz input (1.667v range, pga = 1) 105 105 dbfs 30mhz input (2.5v range, pga = 0) 105 105 dbfs 30mhz input (1.667v range, pga = 1) 105 105 dbfs 70mhz input (2.5v range, pga = 0) 100 100 dbfs 70mhz input (1.667v range, pga = 1) 100 100 dbfs sfdr 1mhz input (2.5v range, pga = 0) 115 115 dbfs 1mhz input (1.667v range, pga = 1) 115 115 dbfs 5mhz input (2.5v range, pga = 0) 100 115 100 115 dbfs 5mhz input (1.667v range, pga = 1) 115 115 dbfs 12.5mhz input (2.5v range, pga = 0) 115 115 dbfs 12.5mhz input (1.667v range, pga = 1) 115 115 dbfs 30mhz input (2.5v range, pga = 0) 115 115 dbfs 30mhz input (1.667v range, pga = 1) 100 115 100 115 dbfs 70mhz input (2.5v range, pga = 0) 110 110 dbfs 70mhz input (1.667v range, pga = 1) 110 110 dbfs parameter conditions min typ max units v cm output voltage i out = 0 1.15 1.25 1.35 v v cm output tempco i out = 0 100 ppm/c v cm line regulation 3.135v v dd 3.465v 1 mv/ v v cm output resistance 1ma | i out | 1ma 2 dy a ic accuracy u w the denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. a in = C1dbfs unless otherwise noted. (note 4) the denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. (note 4) spurious free dynamic range at C 25dbfs dither off spurious free dynamic range at C 25dbfs dither on
ltc2203/ltc2202 5 22032p ltc2203 ltc2202 symbol parameter conditions min typ max min typ max units v dd analog supply voltage 3.135 3.3 3.465 3.135 3.3 3.465 v p shdn shutdown power shdn = v dd , clk = v dd 2 2 mw ov dd output supply voltage 0.5 v dd 0.5 v dd v i vdd analog supply current 64 tbd 42 tbd ma p dis power dissipation 210 tbd 140 tbd mw the denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. (note 4) d igi t al i puts a d digit al outputs u u symbol parameter conditions min typ max units logic inputs (clk, oe, dith, pga, shdn, rand) v ih high level input voltage v dd = 3.3v 2 v v il low level input voltage v dd = 3.3v 0.8 v i in digital input current v in = 0v to v dd 10 a c in digital input capacitance (note 7) 1.5 pf logic outputs ov dd = 3.3v v oh high level output voltage v dd = 3.3v i o = C10a 3.299 v i o = C 200a 3.1 3.29 v v ol low level output voltage v dd = 3.3v i o = 160ua 0.01 v i o = 1.6ma 0.10 0.4 v i source output source current v out = 0v C 50 ma i sink output sink current v out = 3.3v 50 ma ov dd = 2.5v v oh high level output voltage v dd = 3.3v i o = C 200a 2.49 v v ol low level output voltage v dd = 3.3v i o = 1.60ma 0.1 v ov dd = 1.8v v oh high level output voltage v dd = 3.3v i o = C 200a 1.79 v v ol low level output voltage v dd = 3.3v i o = 1.60ma 0.1 v pow er r equir e e ts w u the denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. a in = C1dbfs. (note 9)
prepared for ltc2203/ltc2202 6 22032p t ap analog input t h t d t c t l n C 7 n C 6 n C 5 n C 4 n C 3 clk clkout+ clkoutC d0-d15, of a 22032 td01 n + 1 n + 2 n + 4 n + 3 n ti i g diagra u w w ltc2203 ltc2202 symbol parameter conditions min typ max min typ max units f s sampling frequency 1 25 1 10 mhz t l clk low time duty cycle stabilizer off 18.9 20 500 40 50 500 ns duty cycle stabilizer on 5 20 500 5 50 500 ns t h clk high time duty cycle stabilizer off 18.9 20 500 40 50 500 ns duty cycle stabilizer on 5 20 500 5 50 500 ns t ap sample-and-hold 0 0 ns aperture delay t d clk to data delay c l = 5pf (note 7) 1.3 3.1 4.5 1.3 3.1 4.5 ns t c clk to clkout delay c l = 5pf (note 7) 1.3 3.1 4.5 1.3 3.1 4.5 ns t skew data to clkout skew c l = 5pf (note 7) C 0.6 0 0.6 C 0.6 0 0.6 ns data access time c l = 5pf (note 7) 5 15 5 15 ns bus relinquish time (note 7) 5 15 5 15 ns pipeline 7 7 cycles latency note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd, with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3.3v, f sample = 25mhz (ltc2203), 10mhz (ltc2202), input range = 2.5v p-p with differential drive (pga = 0), unless otherwise speci?ed. note 5: integral nonlinearity is de?ned as the deviation of a code from a best ?t straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from C 1/2lsb when the output code ?ickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2s complement output mode. note 7: guaranteed by design, not subject to test. note 8: recommended operating conditions. ti i g characteristics u w the denotes the speci?cations which apply over the full operating temperature range, otherwise speci?cations are at t a = 25c. (note 4)
ltc2203/ltc2202 7 22032p typical perfor u w ce characteristics a ltc2203: integral nonlinearity (inl) vs output code ltc2203: differential nonlinearity (inl) vs output code ltc2203: ac grounded input histogram (256k samples) ltc2203: 128k point fft, f in = 1mhz, C1dbfs, pga = 0 ltc2203: 128k point fft, f in = 1mhz, C10dbfs, pga = 0 ltc2203: 128k point fft, f in = 1mhz, C20dbfs, pga = 0 code 0 inl error (lsb) 0.0 0.5 1.0 65536 22032 g01 C0.5 C1.0 C2.0 16384 32768 49152 C1.5 2.0 1.5 code 0 C1.0 inl error (lsb) C0.8 C0.4 C0.2 0.0 1.0 0.4 16384 32768 22032 g02 C0.6 0.6 0.8 0.2 49152 65536 output code 32812 0 count 10000 20000 30000 40000 50000 60000 32816 32820 32824 32828 22032 g03 32832 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 go4 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 go5 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 go6 ltc2203: 128k point fft, f in = 5.1mhz, C1dbfs, pga = 0 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 go7 ltc2203: 128k point fft, f in = 5.1mhz, C10dbfs, pga = 0 ltc2203: 128k point fft, f in = 5.1mhz, C20dbfs, pga = 0, internal dither off frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 go8 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 go9
prepared for ltc2203/ltc2202 8 22032p typical perfor u w ce characteristics a ltc2203: 128k point fft, f in = 5.1mhz, C20dbfs, pga = 0, internal dither on ltc2203: 32k point fft, f in = 4.9mhz and 30.1mhz, C7dbfs, pga = 0 ltc2203: 32k point fft, f in = 4.9mhz and 30.1mhz, C15dbfs, pga = 0 ltc2203: sfdr vs input level, f in = 5mhz, pga = 0, dither off ltc2203: sfdr vs input level, f in = 5mhz, pga = 0, dither on ltc2203: 32k point fft, f in = 12.4mhz, C1dbfs, pga = 0 ltc2203: 32k point fft, f in = 12.4mhz, C10dbfs, pga = 0 ltc2203: 32k point fft, f in = 12.4mhz, C20dbfs, pga = 0 ltc2203: sfdr vs input level, f in = 12.7mhz, pga = 0, dither off frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 g10 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 g11 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 g12 input level (dbfs) C80 sfdr (dbc and dbfs) 80 100 120 22032 g13 60 40 C70 C60 C50 C40 C30 C20 C10 0 20 0 140 input level (dbfs) C80 sfdr (dbc and dbfs) 80 100 120 22032 g14 60 40 C70 C60 C50 C40 C30 C20 C10 0 20 0 140 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 g15 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 g16 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 g17 input level (dbfs) C80 sfdr (dbc and dbfs) 80 100 120 22032 g18 60 40 C70 C60 C50 C40 C30 C20 C10 0 20 0 140
ltc2203/ltc2202 9 22032p typical perfor u w ce characteristics a ltc2203: sfdr vs input level, f in = 12.7mhz, pga = 0, dither on ltc2203: 32k point fft, f in = C30mhz, C1dbfs, pga = 1 ltc2203: 32k point fft, f in = 30mhz, C10dbfs, pga = 1 ltc2203: 32k point fft, f in = C30mhz, C20dbfs, pga = 1 ltc2203: sfdr vs input level, f in = 30.1mhz, pga = 0, dither off ltc2203: sfdr vs input level, f in = 30.1mhz, pga = 0, dither on ltc2203: 32k point fft, f in = 70.1mhz, C1dbfs, pga = 1 ltc2203: 32k point fft, f in = 70.1mhz, C10dbfs, pga = 1 ltc2203: 32k point fft, f in = 70.1mhz, C20dbfs, pga = 1 input level (dbfs) C80 sfdr (dbc and dbfs) 80 100 120 22032 g19 60 40 C70 C60 C50 C40 C30 C20 C10 0 20 0 140 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 g20 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 g21 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 g22 input level (dbfs) C80 sfdr (dbc and dbfs) 80 100 120 22032 g23 60 40 C70 C60 C50 C40 C30 C20 C10 0 20 0 140 input level (dbfs) C80 sfdr (dbc and dbfs) 80 100 120 22032 g24 60 40 C70 C60 C50 C40 C30 C20 C10 0 20 0 140 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 g25 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 g26 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 g27
prepared for ltc2203/ltc2202 10 22032p typical perfor u w ce characteristics a ltc2203: 32k point fft, f in = 44.9mhz and 70.1mhz, C7dbfs, pga = 0 ltc2203: 32k point fft, f in = 44.9mhz and 70.1mhz, C15dbfs, pga = 0 ltc2203: sfdr vs input level, f in = 70.1mhz, pga = 0, dither off ltc2203: sfdr vs input level, f in = 70.1mhz, pga = 0, dither on ltc2203: sfdr (hd2 and hd3) vs input frequency ltc2203: snr vs input frequency ltc2203: snr and sfdr vs sample rate ltc2203: snr and sfdr vs supply voltage (vdd), f in = 5mhz ltc2203: i vdd vs sample rate, 5mhz sine wave, C1dbfs frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 g28 frequency(mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C10 C30 C50 C70 C90 C110 C130 C40 2 6 C20 C60 4 8 10 12 22032 g29 input level (dbfs) C80 C70 C60 C50 C40 C30 C20 C10 0 sfdr (dbc and dbfs) 80 100 120 22023 g30 60 40 20 0 140 input level (dbfs) C80 sfdr (dbc and dbfs) 80 100 120 22032 g31 60 40 C70 C60 C50 C40 C30 C20 C10 0 20 0 140 input frequency (mhz) 0 sfdr (dbc) 85 90 95 60 100 22023 g32 80 75 70 20 40 80 100 105 110 input frequency ((mhz) 0 73 snr (dbfs) 74 76 77 78 80 82 22023 g3 3 75 40 20 100 120 60 140 79 80 81 sample rate (msps) 0 75 snr and sfdr (dbfs) 80 90 95 100 110 5 25 35 22023 g34 85 105 20 45 50 10 15 30 40 supply voltage (v) 2.8 snr sfdr (dbfs) 95 100 105 3.4 3.5 22023 g35 90 85 2.9 3.0 3.1 3.2 3.3 3.6 80 75 110 sample rate (msps) 0 i vdd (ma) 65 70 75 20 22023 g36 60 55 50 5 10 15 25
ltc2203/ltc2202 11 22032p typical perfor u w ce characteristics a ltc2203: normalized full scale vs temperature, internal reference, 5 units ltc2203: offset voltage vs temperature, 5 units ltc2203: sfdr vs input common mode voltage, f in = 5mhz, C1dbfs, pga = 0 ltc2202: integral nonlinearity (inl) vs output code ltc2202: differential nonlinearity (dnl) vs output code ltc2202: ac grounded input histogram (256k samples) ltc2202: 128k point fft, f in = 5.1mhz, C1dbfs, pga = 0 ltc2202: 128k point fft, f in = 5.1mhz, C10dbfs, pga = 0 ltc2202: 128k point fft, f in = 5.1mhz, C20dbfs, pga = 0, internal dither off temperature ( c) C40 0.99 normalized full scale 0.995 1 1.005 1.01 C20 0 20 4 0 22023 g37 60 80 temperature (?c) C40 offset voltage (mv) 2 4 6 20 60 22023 g38 0 C2 C20 0 40 80 C4 C6 input common mode voltage (v) 0.5 60 sfdr (dbc) 70 80 90 0.75 1 1.25 1.50 22023 g39 1.75 100 110 65 75 85 95 105 2 code 0 inl error (lsb) 0 0.5 1.0 65536 22023 g4 0 C0.5 C1.0 C2.0 16384 32768 49152 C1.5 2.0 1.5 code 0 1.0 inl error (lsb) 0.8 0.4 0.2 0 1.0 0.4 16384 32768 22023 g41 0.6 0.6 0.8 0.2 49152 65536 output code 32793 count 40000 35000 30000 25000 15000 5000 45000 50000 32797 22023 g42 20000 10000 0 32801 32805 32809 frequency (mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C40 1 3 4 C20 C60 C130 C110 C90 C10 C50 C30 C70 2 5 22023 g43 frequency (mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C40 1 3 4 C20 C60 C130 C110 C90 C10 C50 C30 C70 2 5 22023 g44 frequency (mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C40 1 3 4 C20 C60 C130 C110 C90 C10 C50 C30 C70 2 5 22023 g45
prepared for ltc2203/ltc2202 12 22032p typical perfor u w ce characteristics a ltc2203: 128k point fft, f in = 5.1mhz, C20dbfs, pga = 0, internal dither on ltc2202: 32k point fft, f in = 5.1mhz and 15.2mhz, C7dbfs, pga = 0 ltc2202: 32k point fft, f in = 5.1mhz and 15.2mhz, C15dbfs, pga = 0 ltc2202: sfdr vs input level, f in = 5mhz, pga = 0, dither off ltc2202: sfdr vs input level, f in = 5mhz, pga = 0, dither on ltc2202: 32k point fft, f in = 12.4mhz, C1dbfs, pga = 0 ltc2202: 32k point fft, f in = 12.4mhz, C10dbfs, pga = 0 ltc2202: 32k point fft, f in = 12.4mhz, C20dbfs, pga = 0 ltc2202: sfdr vs input level, f in = 12.4mhz, pga = 0, dither off frequency (mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C40 1 3 4 C20 C60 C130 C110 C90 C10 C50 C30 C70 2 5 22023 g46 frequency (mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C40 1 3 4 C20 C60 C130 C110 C90 C10 C50 C30 C70 2 5 22023 g47 frequency (mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C40 1 3 4 C20 C60 C130 C110 C90 C10 C50 C30 C70 2 5 22023 g48 input level (dbfs) C80 0 sfdr (dbc and dbfs) 20 40 60 80 C60 C40 C20 0 22023 g49 100 120 C70 C5 0 C30 C10 input level (dbfs) C80 0 sfdr (dbc and dbfs) 40 20 60 80 100 C60 C40 C20 0 22023 g50 120 140 C70 C50 C30 C10 frequency (mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C40 1 3 4 C20 C60 C130 C110 C90 C10 C50 C30 C70 2 5 22023 g51 frequency (mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C40 1 3 4 C20 C60 C130 C110 C90 C10 C50 C30 C70 2 5 22023 g52 frequency (mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C40 1 3 4 C20 C60 C130 C110 C90 C10 C50 C30 C70 2 5 22023 g53 input level (dbfs) C80 0 sfdr (dbc and dbfs) 20 40 60 80 C60 C40 C20 0 22023 g54 100 120 C70 C5 0 C30 C10
ltc2203/ltc2202 13 22032p typical perfor u w ce characteristics a ltc2202: 32k point fft, f in = 30.5mhz, C1dbfs, pga = 1 ltc2202: 32k point fft, f in = 30.5mhz, C10dbfs, pga = 1 ltc2202: 32k point fft, f in = 30.5mhz, C20dbfs, pga = 1 ltc2202: sfdr vs input level, f in = 30.1mhz, pga = 0, dither off ltc2202: sfdr vs input level, f in = 30.1mhz, pga = 0, dither on ltc2202: 32k point fft, f in = 70.1mhz, C1dbfs, pga = 1 ltc2202: 32k point fft, f in = 70.1mhz, C10dbfs, pga = 1 ltc2202: 32k point fft, f in = 70.1mhz, C20dbfs, pga = 1 ltc2202: 32k point fft, f in = 60.2mhz and 70.1mhz, C7dbfs, pga = 0 frequency (mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C40 1 3 4 C20 C60 C130 C110 C90 C10 C50 C30 C70 2 5 22023 g55 frequency (mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C40 1 3 4 C20 C60 C130 C110 C90 C10 C50 C30 C70 2 5 22023 g56 frequency (mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C40 1 3 4 C20 C60 C130 C110 C90 C10 C50 C30 C70 2 5 22023 g57 input level (dbfs) C80 0 sfdr (dbc and dbfs) 40 20 60 80 100 C60 C40 C20 0 22023 g58 120 140 C70 C50 C30 C10 input level (dbfs) C80 0 sfdr (dbc and dbfs) 40 20 60 80 100 C60 C40 C20 0 22023 g59 120 140 C70 C50 C30 C10 frequency (mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C40 1 3 4 C20 C60 C130 C110 C90 C10 C50 C30 C70 2 5 22023 g60 frequency (mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C40 1 3 4 C20 C60 C130 C110 C90 C10 C50 C30 C70 2 5 22023 g61 frequency (mhz) 0 C140 amplitude (dbfs) C120 C100 C80 0 C40 1 3 4 C20 C60 C130 C110 C90 C10 C50 C30 C70 2 5 22023 g62 frequency (mhz) C140 amplitude (dbfs) C120 C100 C80 0 C40 C20 C60 C130 C110 C90 C10 C50 C30 C70 22023 g63 0 2 4
prepared for ltc2203/ltc2202 14 22032p typical perfor u w ce characteristics a ltc2202: 32k point fft, f in = 60.2mhz and 70.1mhz, C15dbfs, pga = 0 ltc2202: sfdr vs input level, f in = 70.1mhz, pga = 0, dither off ltc2202: sfdr vs input level, f in = 70.1mhz, pga = 0, dither on ltc2202: sfdr (hd2 and hd3) vs input frequency ltc2202: snr vs input frequency ltc2202: snr and sfdr vs sample rate ltc2202: snr and sfdr vs supply voltage (vdd), f in = 5mhz ltc2202: i vdd vs sample rate, 5mhz sine wave, C1dbfs ltc2202: normalized full scale vs temperature, internal reference, 5 units frequency (mhz) C140 amplitude (dbfs) C120 C100 C80 0 C40 C20 C60 C130 C110 C90 C10 C50 C30 C70 22023 g64 0 2 4 input level (dbfs) C80 0 sfdr (dbc and dbfs) 40 20 60 80 100 C60 C40 C20 0 22023 g65 120 140 C70 C50 C30 C10 input level (dbfs) C80 0 sfdr (dbc and dbfs) 40 20 60 80 100 C60 C40 C20 0 22023 g66 120 140 C70 C50 C30 C10 input frequency (mhz) 0 sfdr(dbc) 85 90 95 60 100 22023 g67 80 75 70 20 40 80 100 105 110 input frequency (mhz) 0 73 snr (dbfs) 74 76 77 78 80 82 22023 g6 8 75 40 20 100 120 60 140 79 80 81 sample rate (msps) 0 100 105 110 16 22023 g6 9 95 90 4 8 12 20 85 80 75 snr and sfdr (dbfs) supply voltage (v) 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 snr sfdr (dbfs) 95 100 105 22023 g70 90 85 80 75 110 sample rate (msps) 0 i vdd (ma) 46 48 50 8 22023 g71 44 42 45 47 49 43 41 40 2 4 6 10 temperature ( c) C40 0.99 normalized full scale 0.995 1 1.005 1.01 C20 0 20 4 0 22023 g72 60 80
ltc2203/ltc2202 15 22032p typical perfor u w ce characteristics a temperature (?c) C40 offset voltage (mv) 2 4 6 20 60 22023 g7 3 0 C2 C20 0 40 80 C4 C6 input common mode voltage (v) 0.5 60 sfdr (dbc) 70 80 90 0.75 1 1.25 1.50 22023 g74 1.75 100 110 65 75 85 95 105 2 sense (pin 1): reference mode select and external reference input. tie sense to v dd to select the internal 2.5v bandgap reference. an external reference of 2.5v or 1.25v may be used; both reference values will set a full scale adc range of 2.5v (pga = 0). v cm (pin 2): 1.25v output. optimum voltage for input com - mon mode. must be bypassed to ground with a minimum of 2.2f. ceramic chip capacitors are recommended. v dd (pins 3, 4, 12, 13, 14): 3.3v analog supply pin. bypass to gnd with 0.1f ceramic chip capacitors. gnd (pins 5, 8, 9, 11, 15, 48, 49): adc power ground. a in + (pin 6): positive differential analog input. a in C (pin 7): negative differential analog input. clk (pin 10): clock input. the hold phase of the sample- and-hold circuit begins on the falling edge. shdn (pin 16): power shutdown pin. shdn = low results in normal operation. shdn = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. dith (pin 17): internal dither enable pin. dith = low disables internal dither. dith = high enables internal dither. refer to internal dither section of this data sheet for details on dither operation. db0-db15 (pins 18-22, 26-28, 32-35 and 39-42): digital outputs. d15 is the msb. ognd (pins 23, 31 and 38): output driver ground. ov dd (pins 24, 25, 36, 37): positive supply for the output drivers. bypass to ground with 0.1f capacitor. clkout C (pin 29): data valid output. clkout C will toggle at the sample rate. latch the data on the falling edge of clkout C . clkout + (pin 30): inverted data valid output. clkout + will toggle at the sample rate. latch the data on the rising edge of clkout + . of (pin 43): over/under flow digital output. of is high when an over or under ?ow has occurred. ? o ? e (pin 44): output enable pin. low enables the digital output drivers. high puts digital outputs in hi-z state. u u u pi fu ctio s ltc2202: offset voltage vs temperature, 5 units ltc2202: sfdr vs input common mode voltage, f in = 5mhz, C1dbfs, pga = 0
prepared for ltc2203/ltc2202 16 22032p block diagra w figure 1. functional block diagram adc clocks differential input low jitter clock driver dither signal genera tor first pipelined adc st age fifth pipelined adc st ag e four th pipelined adc st ag e second pipelined adc st age clk correction logic and shift register dith m0de ognd clkout+ clkout C of d15 d14 ov dd d1 d0 22032 f01 input s/h a in C a in + third pipelined adc st ag e output drivers control logic pga rand shdn ? ? ? v dd gnd pga sense v cm buffer adc reference vol t age reference range select mode (pin 45): output format and clock duty cycle stabilizer selection pin. connecting mode to 0v selects offset binary output format and disables the clock duty cycle stabilizer. connecting mode to 1/3v dd selects offset binary output format and enables the clock duty cycle sta - bilizer. connecting mode to 2/3v dd selects 2s complement output format and enables the clock duty cycle stabilizer. connecting mode to v dd selects 2s complement output format and disables the clock duty cycle stabilizer. rand (pin 46): digital output randomization selection pin. rand low results in normal operation. rand high selects d1-d15 to be exclusive-ored with d0 (the lsb). the output can be decoded by again applying an xor operation between the lsb and all other bits. the mode of operation reduces the effects of digital output interference. pga (pin 47): programmable gain ampli?er control pin. low selects a front-end gain of 1, input range of 2.5v p-p . high selects a front-end gain of 1.5, input range of 1.667v p-p . gnd (exposed pad, pin 49): adc power ground. the ex - posed pad on the bottom of the package must be soldered to ground. u u u pi fu ctio s
ltc2203/ltc2202 17 22032p dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n+d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band lim - ited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components, except the ?rst ?ve harmonics. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = C 20log ( (v 2 2 + v 3 2 + v 4 2 + ... v n 2 )/v 1 ) where v 1 is the rms amplitude of the fundamental fre - quency and v 2 through v n are the amplitudes of the second through nth harmonics. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 3nd order imd terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). the 3rd order imd is de?ned as the ration of the rms value of either input tone to the rms value of the largest 3rd order imd product. spurious free dynamic range (sfdr) the ratio of the rms input signal amplitude to the rms value of the peak spurious spectral component expressed in dbc. sfdr may also be calculated relative to full scale and expressed in dbfs. full power bandwidth the full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when clk reaches mid-supply to the instant that the input signal is held by the sample-and- hold circuit. aperture delay jitter the variation in the aperture delay time from convertion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C 20log (2 ? f in ? t jitter ) applica tio s i for a tio w u u u
prepared for ltc2203/ltc2202 18 22032p converter operation the ltc2203/ltc2202 are cmos pipelined multistep con - verters with a front-end pga. as shown in figure 1, the con - verter has ?ve pipelined adc stages; a sampled analog input will result in a digitized value seven cycles later (see the timing diagram section). the analog input is differential for improved common mode noise immunity and to maximize the input range. additionally, the differential input drive will reduce even order harmonics of the sample-and-hold circuit. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage ampli?er. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is ampli?ed and output by the residue ampli?er. successive stages oper - ate out of phase so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. the phase of operation is determined by the state of the clk input pin. when clk is high, the analog input is sampled differen - tially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that clk transitions from high to low, the voltage on the sample capacitors is held. while clk is low, the held input voltage is buffered by the s/h ampli?er which drives the ?rst pipelined adc stage. the ?rst stage acquires the output of the s/h ampli?er during the low phase of clk. when clk goes back high, the ?rst stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when clk goes low, the second stage produces its residue which is acquired by the third stage. an identi - cal process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the ?fth stage for ?nal evaluation. each adc stage following the ?rst has additional range to accommodate ?ash and ampli?er offset errors. results from all of the adc stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer. applica tio s i for a tio w u u u sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2203/ ltc2202 cmos differential sample and hold. the differ - ential analog inputs are sampled directly onto sampling capacitors (c sample ) through nmos transitors. the capacitors shown attached to each input (c parasitic ) are the summation of all other capacitance associated with each input. during the sample phase when clk is high, the nmos transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. when clk transitions from high to low, the sampled input voltage is held on the sampling capacitors. during the hold phase when clk is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as clk transitions from low to high, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time at the input of the converter. if the change between the last sample and figure 2. equivalent input circuit c sample 9.1pf v dd v l tc220 clk 3/02 a in + 22032 f02 c sample 9.1pf v dd a in C c p arasitic 1.8pf c p arasitic 1.8pf
ltc2203/ltc2202 19 22032p the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. common mode bias the adc sample-and-hold circuit requires differential drive to achieve speci?ed performance. each input may swing 0.625v for the 2.5v range (pga = 0) or 0.417v for the 1.667v range (pga = 1), around a common mode voltage of 1.25v. the v cm output pin (pin 3) is designed to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with 2.2f or greater. input drive impedence as with all high performance, high speed adcs the dynamic performance of the ltc2203/ltc2202 can be in?uenced by the input drive circuitry, particularly the second and third harmonics. source impedance and input reactance can in?uence sfdr. at the rising edge of clk the sample and hold circuit will connect the 9.1pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when clk falls, hold - ing the sampled input on the sampling capacitor. ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f clk ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance it is recomended to have a source impedence of 100 or less for each input. the source impedence should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits figure 3 shows the ltc2203/ltc2202 being driven by an rf transformer with a center-tapped secondary. the secondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the adc. source impedance greater than 50 can reduce the input bandwidth and increase high frequency distortion. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequen - cies below 1mhz. center-tapped transformers provide a convenient means of dc biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. figure 4 shows transformer coupling using a transmis - sion line balun transformer. this type of transformer has much better high frequency response and balance than ?ux coupled center tap transformers. coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.25v. applica tio s i for a tio w u u u figure 3. single-ended to differential conversion using a transformer. recommended for input frequencies from 1mhz to 50mhz a in + a in C 12pf 12pf 12pf v cm l tc2203/02 analog input t1 1:1 t1 = coilcraft wbci-it or ma/com etc1-1t , resistors, cap acitors are 0402 p ackage size except 2.2 f 22032 f03 figure 4. using a transmission line balun transformer. recommended for input frequencies from 50mhz to 250mhz 0.1 f a in + a in C 4.7pf 2.2 f 4.7pf 4.7pf v cm l tc2203/02 analog input 0.1 f 0.1 f t1 1:1 t1 = ma/com etc1-1-13 resistors, cap acitors are 0402 p ackage siz e except 2.2f 22032 f04
prepared for ltc2203/ltc2202 20 22032p figure 5 demonstrates the use of an ltc1994 differential ampli?er to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp will limit the sfdr at high input frequencies. the 25 resistors and 12pf capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. reference operation figure 6 shows the ltc2203/ltc2202 reference circuitry consisting of a 2.5v bandgap reference, a programmable gain ampli?er and control circuit. the ltc2203/ltc2202 has three modes of reference operation: internal refer - ence, 1.25v external reference or 2.5v external reference. to use the internal reference, tie the sense pin to v dd . to use the external reference, simply apply either a 1.25v or 2.5v reference voltage to the sense input pin. both 1.25v and 2.5v applied to snese will result in a full scale range of 2.5 v p-p (pga = 0). a 1.25v output, v cm , is provided for a common mode bias for input drive circuitry. an external bypass capacitor is required for the v cm output. this provides a high frequency low impedance path to ground for internal and external circuitry. this is also the compensation capacitor for the reference; it will not be stable without this capacitor. the minimum value required for stability is 2.2f. applica tio s i for a tio w u u u the internal programmable gain ampli?er provides the internal reference voltage for the adc. this ampli?er has very stringent settling requirements and is not accessible for external use. figure 5. dc coupled input with differential ampli?er v cm l tc2203/02 22032 f05 C C + + cm 499 ? 100pf 100pf 100pf 499 ? 523 ? 499 ? 53.6 ? a in + a in C figure 6. reference circuit pga 1.25v sense v cm buffer internal adc reference range select and gain control 2.5v bandgap reference 2.2 f t ie to v dd to use internal 2.5v reference or input for external 2.5v reference or input for external 1.25v reference 22032 f07 l tc2203/0 2 figure 7. a 2.25v range adc with an external 2.5v reference pga pin the pga pin selects between two gain settings for the adc front-end. pga = 0 selects an input range of 2.5v p-p ; pga = 1 selects an input range of 1.667v p-p . the 2.5v input range has the best snr; however, the distortion will be v cm sense 1.25v 3.3v 2.2 f 2.2 f 1 f 22032 f08 l tc2203/02 l tc1461-2. 5 2 6 4 the sense pin can be driven 5% around the nominal 2.5v or 1.25v external reference input. this adjustment range can be used to trim the adc gain error or other system gain errors. when selecting the internal reference, the sense pin should be tied to v dd as close to the converter as possible. if the sense pin is driven externally it should be bypassed to ground as close to the device as possible with at least a 1f ceramic capacitor.
ltc2203/ltc2202 21 22032p applica tio s i for a tio w u u u an on-chip clock duty cycle stabilizer may be activated if the input clock does not have a 50% duty cycle. this circuit uses the falling edge of clk pin to sample the analog input. the rising edge of clk is ignored and an internal rising edge is generated by a phase-locked loop. the input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin must be connected to 1/3v dd or 2/3v dd using external resistors. the lower limit of the ltc2203/ltc2202 sample rate is determined by droop of the sample and hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the speci?ed minimum operating frequency for the ltc2203/ltc2202 is 1msps. digital outputs digital output buffers figure 9 shows an equivalent circuit for a single output buffer in cmos mode. each buffer is powered by ov dd and ognd, isolated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 to external circuitry and eliminates the need for external damping resistors. figure 8. sinusoidal single-ended clk drive clk 0.1 f 0.1 f 4.7 f 1k 1k ferrite bead clean 3.3v supply sinusoidal clock input 22032 f09 nc7svu04 l tc2203/02 56 ? higher for input frequencies above 100mhz. for applica - tions with high input frequencies, the low input range will have improved distortion; however, the snr will be 2.4db worse. see the typical performance curves section. driving the clock input the clk input can be driven directly with a cmos or ttl level signal. a sinusoidal clock can also be used along with a low-jitter squaring circuit before the clk pin (see figure 8). the noise performance of the ltc2203/2202 can depend on the clock signal quality as much as on the analog input. any noise present on the clock signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical, such as when digi - tizing high input frequencies, use as large an amplitude as possible. also, if the adc is clocked with a sinusoidal signal, ?lter the clk signal to reduce wideband noise and distortion products generated by the source. maximum and minimum conversion rates the maximum conversion rate for the ltc2203 is 25msps. the maximum conversion rate for the ltc2202 is 10msps. for the adc to operate properly the clk signal should have a 50% (5%) duty cycle. each half cycle must have at least 18.9ns for the ltc2203 internal circuitry to have enough settling time for proper operation. for the ltc2202, each half cycle must be at least 40ns. figure 9. equivalent circuit for a digital output buffer l tc2203/02 22032 f10 ov dd v dd v dd 0.1 f typical data output ognd 43 ? ov dd 0.5v to 3.6v predriver logic data from la tch
prepared for ltc2203/ltc2202 22 22032p output clock the adc has a delayed version of the clk input available as a digital output. both a noninverted version, clkout + and an inverted version clkout C are provided. the clkout + /clkout C can be used to synchronize the con - verter data to the digital system. this is necesary when using a sinusoidal clock. data can be latched on the ris - ing edge of clkout+ or the falling edge of clkoutC. clkout+ falls and clkoutC rises as the data outputs are updated. digital output randomizer interference from the adc digital outputs is sometimes unavoidable. interference from the digital outputs may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can result in discernible unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise ?oor for a large reduction in unwanted tone amplitude. the digital output is randomized by applying an exclu - sive-or logic operation between the lsb and all other data output bits. to decode, the reverse operation is applied; that is, an exclusive-or operation is applied between the lsb and all other bits. the lsb, of and clkout output are not affected. the output randomizer function is active when the rand pin is high. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied as with all high speed/high resolution converters, the digital output loading can affect the performance. the digital outputs of the ltc2203/ltc2202 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. the output should be buffered with a device such as a alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. a resistor in series with the output may be used but is not required since the adc has a series resistor of 43 on chip. lower ov dd voltages will also help reduce interference from the digital outputs. data format the ltc2203/ltc2202 parallel digital output can be selected for offset binary or 2s complement format. the format is selected with the mode pin. this pin has a four level logic input, centered at 0, 1/3v dd , 2/3v dd and v dd . an external resistor divider can be user to set the 1/3v dd and 2/3v dd logic levels. table 1 shows the logic states for the mode pin. table 1. mode pin function clock duty mode output format cycle stabilizer 0(gnd) offset binary off 1/3v dd offset binary on 2/3v dd 2s complement on v dd 2s complement off over?ow bit an over?ow output bit (of) indicates when the converter is over-ranged or under-ranged. a logic high on the of pin indicates an over?ow or under?ow. applica tio s i for a tio w u u u
ltc2203/ltc2202 23 22032p internal dither mode can be enabled to randomize the inputs location on the adc transfer curve, resulting in improved sfdr for low signal levels. as shown in figure 12, the output of the sample-and-hold ampli?er is summed with the output of a dither dac. the dither dac is driven by a long sequence pseudo-random number generator; the random number fed to the dither dac is also subtracted from the adc result. if the dither dac is precisely calibrated to the adc, very little of the dither signal will be seen at the output. the dither signal that does leak through will appear as white noise. the dither dac is calibrated to result in less than 0.5db elevation in the noise ?oor of the adc, as compared to the noise ?oor with dither off. applica tio s i for a tio w u u u to the same power supply as for the logic being driven. for example, if the converter is driving a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. in cmos mode ov dd can be powered with any logic voltage up to 3.6v. ognd can be powered with any voltage from ground up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . internal dither the ltc2203/ltc2202 are 16-bit adcs with very linear transfer functions; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. small errors in the transfer function are usually a result of adc element mismatches. an optional ? ? ? clkout of d15/d0 d14/d0 d2/d0 d1/d0 d0 d0 d1 rand = high, scramble enabled d2 d14 d15 of clkout rand 22032 f11 l tc2203/02 figure 10. functional equivalent of digital output randomizer figure 11. descrambling a scrambled digital output ? ? ? d1 d0 d2 d14 d15 l tc2203/02 pc board fpga clkout of d15/d0 d14/d0 d2/d0 d1/d0 d0 22032 f12
prepared for ltc2203/ltc2202 24 22032p grounding and bypassing the ltc2203/ltc2202 require a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. the pinout of the ltc2203/ltc2202 has been optimized for a ?owthrough layout so that the interaction between inputs and digital outputs is minimized. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd, v cm , and ov dd pins. bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. applica tio s i for a tio w u u u the ltc2203/ltc2202 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the ltc2203/ltc2202 is transferred from the die through the bottom-side exposed pad. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. it is critical that the exposed pad and all ground pins are connected to a ground plane of suf?cient area with as many vias as possible. figure 12. functional equivalent block diagram of internal dither circuit ain + ain C s/h amp digit al summa tio n output drivers mul tibit deep pseudo-random number genera to r 16-bit pipelined adc core precision dac clock/duty cycle control clkout+ clkoutC of d15 ? ? ? d0 clk dither enable high = dither on low = dither off dith analog input 22032 f13 l tc2203/02
ltc2203/ltc2202 25 22032p information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u package descriptio 7.00 0.10 (4 sides) note: 1. dra wing conforms to jedec p ackage outline mo-220 v aria tion (wkkd-2 ) 2. dra wing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed p ad on bottom of p ackage do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if presen t 5. exposed p ad shall be solder pla ted 6. shaded area is only a reference for pin 1 loca tion on the top and bottom of p ackag e pin 1 top mark (see note 6) pin 1 chamfer 0.40 0.10 48 47 1 2 bottom viewexposed pa d 5.15 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (uk48) qfn 1103 recommended solder p ad pitch and dimension s 0.70 0.05 5.15 0.05 (4 sides) 6.10 0.05 7.50 0.05 0.25 0.05 0.50 bsc package outline uk package 48-lead plastic qfn (7mm 7mm) (reference ltc dwg # 05-08-1704) applica tio s i for a tio w u u u evaluation boards
prepared for ltc2203/ltc2202 26 22032p related parts part number description comments ltc1747 12-bit, 80msps adc 72db snr, 87db sfdr, 48-pin tssop package ltc1748 14-bit, 80msps adc 76.3db snr, 90db sfdr, 48-pin tssop package ltc1749 12-bit, 80msps wideband adc up to 500mhz if undersampling, 87db sfdr ltc1750 14-bit, 80msps wideband adc up to 500mhz if undersampling, 90db sfdr lt1993 low distortion and noise fixed gain (gain = 2, 4, 10) differential ampli?er lt1994 low distortion and noise 2.375v to 12.6v supplies, adjustable gain, adjustable output differential ampli?er common mode voltage ltc2204 16-bit, 40msps adc 350mw, 79db snr, 100db sfdr ltc2205 16-bit, 65msps adc 450mw, 79db snr, 100db sfdr ltc2206 16-bit, 80msps adc 650mw, 78db snr, 100db sfdr ltc2207 16-bit, 105msps adc 850mw, 78db snr, 100db sfdr ltc2208 16-bit, 130msps adc 1200mw, 78db snr, 100db sfdr ltc2220 12-bit, 170msps adc 890mw, 67.5db snr, 9mm x 9mm qfn package ltc2220-1 12-bit, 185msps adc 910mw, 67.5db snr, 9mm x 9mm qfn package ltc2249 14-bit, 65msps adc 230mw, 73db snr, 5mm x 5mm qfn package ltc2250 10-bit, 105msps adc 320mw, 61.6db snr, 5mm x 5mm qfn package ltc2251 10-bit, 125msps adc 395mw, 61.6db snr, 5mm x 5mm qfn package ltc2252 12-bit, 105msps adc 320mw, 70.2db snr, 5mm x 5mm qfn package ltc2253 12-bit, 125msps adc 395mw, 70.2db snr, 5mm x 5mm qfn package ltc2254 14-bit, 105msps adc 320mw, 72.5db snr, 5mm x 5mm qfn package ltc2255 14-bit, 125msps adc 395mw, 72.4db snr, 5mm x 5mm qfn package ltc2299 dual 14-bit, 80msps adc 445mw, 73db snr, 9mm x 9mm qfn package lt5512 dc-3ghz high signal level dc to 3ghz, 21dbm iip3, integrated lo buffer downconverting mixer lt5514 ultralow distortion if ampli?er/adc 450mhz 1db bw, 47db oip3, digital gain control 10.5db to 33db in 1.5db/step driver with digitally controlled gain lt5521 10 mhz to 3700 mhz high linearity 24.2dbm iip3 at 1.95 ghz, nf = 12.5db, 3.15v to 5.25v supply, single-ended lo upconverting mixer port operation lt5522 600mhz to 2.7ghz high linearity 4.5v to 5.25v supply, 25dbm iip3 at 900mhz, downconverting mixer nf = 12.5db, 50 single-ended rf and lo ports lt5527 400 mhz to 3.7ghz high signal level 24.5 dbm iip3 at 900mhz, nf = 11.6db, 4.5v to 5.25v supply, single-ended rf and lo downconverting mixer ports linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 o fax : (408) 434-0507 #o# www.linear.com ? linear technology corporation 2005 lt/lwi/tp 0905 500 ? printed in usa

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